Various configurations of memory management units are known in the art. Some configurations are illustrated in U.S. patent application 20020062427 of Chauvel et al., titled “Priority arbitration based on current task and MMU” and U.S. Pat. No. 5,835,962 of Chang, et al, titled “Parallel access micro-TLB to speed up address translation”, both being incorporated herein by reference.
Modern processors access both cache memory modules and so caller higher level or external memory modules. The cache memory modules are usually accessed by virtual addresses while external memory modules are accessed by providing physical addresses. Typically, virtual addresses provided by a processor are translated to physical addresses by components other than the processor. U.S. patent application 20020082824 of Neiger al et., titled “virtual translation lookaside buffer”; U.S. patent application 20040117587 of Arimilli et al., titled “Hardware managed virtual-to-physical address translation mechanism” and U.S. patent application 20040143720 of Mansell, et al., titled “Apparatus and method for controlling access to a memory”, all being incorporated herein by reference describe various address translation techniques. There is a need to provide an efficient memory management unit capable of performing an effective address translation
In order to increase the reliability of systems various techniques were suggested. U.S. patent application 20030140245 of Dahan et al., titled “Secure mode for processors supporting MMU and interrupts”, which is incorporated herein by reference, describes a system and method in which a secured operational mode is enabled. Another technique involves restricting access to various registers and also preventing a user form utilizing certain instructions, by defining multiple privilege levels. Typically, these levels include a user privilege level and a supervisor privilege level, the latter being higher than the former. There is a need to provide an efficient memory management unit capable of program protection and a method thereof.
Modern processors usually are capable of performing task switches. U.S. Pat. No. 6,542,991 of Joy et al., titled “Multiple-thread processor with single-thread interface shared among threads” which is incorporated herein by reference describes a task switching processor connected to a memory management unit. Typically, a task switch is time consuming and requires to exchange many control signals, information and the like over data and instruction buses. There is a need to provide an efficient memory management unit capable of performing an efficient task switch.